Key facts
Production status: Active
Release date: 2024-10-10
Cores / Threads: 96 / 192
Base clock: 2600 MHz
Turbo clock: 4500 MHz
TDP: -
Process: 4 nm
Codename: Turin
Generation: EPYC (Zen 5 (Turin))
All available specs
| Field | Value |
|---|---|
| name | EPYC 9655P |
| Socket | AMD Socket SP5 |
| Foundry | TSMC |
| Process Size | 4 nm |
| Transistors | 99,780 million |
| Die Size | 12x 70.6 mm² |
| Package | FC-LGA6096 |
| Market | Server/Workstation |
| Production Status | Active |
| Release Date | Oct 10th, 2024 |
| Part# | 100-000001522 |
| Frequency | 2.6 GHz |
| Turbo Clock | up to 4.5 GHz |
| Base Clock | 100 MHz |
| Multiplier | 26.0x |
| Multiplier Unlocked | No |
| Codename | Turin |
| Generation | EPYC (Zen 5 (Turin)) |
| Memory Support | DDR5 |
| ECC Memory | Yes |
| # of Cores | 96 |
| # of Threads | 192 |
| SMP # CPUs | 1 |
| Cache L1 | 80 KB (per core) |
| Cache L2 | 1 MB (per core) |
| Features | MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, SSE4.1, SSE4.2, AES, AVX, AVX2, AVX-512, AVX-VNNI, VNNI/VEX, BMI1, BMI2, BFloat16, SHA, F16C, FMA3, AMD64, EVP, AMD-V, SMAP, SMEP, X2AVIC, AIBRS, SEV-SNP, 5-level NPT, SMT, Precision Boost 2 |
| Notes | CXL 2.0 supports Type 3 devices which can provide significant increases to system attached DRAM capacity. SEV-SNP security features extend to Type 3 devices.AMD's "Turin" CPUs can be configured for DDR5 6400 MT/s with 1 DIMM per channel (1DPC) in specific scenarios, but 6000 MT/s is the official supported rating for the SP5 platform with firmware updates provided. |
| Rated Speed | 6000 MT/s |
| Memory Bus | Twelve-channel |
| Memory Bandwidth | 576.0 GB/s |
| Launch Price | $10,811 |
| PCI-Express | Gen 5, 128 Lanes (CPU only) |
| Cache L3 | 384 MB (shared) |
| Configurable TDP | 320-400 W |
| I/O Process Size | 6 nm |
| CXL | Gen 2.0 |
| 2DPC Rated Speed | 4400 MT/s |