Key facts
Production status: Active
Release date: 2020-04-14
Cores / Threads: 32 / 64
Base clock: 1100 MHz
Turbo clock: 3000 MHz
TDP: 85 W
Process: 7 nm
Codename: Rome
Generation: EPYC (Zen 2 (Rome))
All available specs
| Field | Value |
|---|---|
| name | EPYC 7D12 |
| Socket | AMD Socket SP3 |
| Foundry | TSMC |
| Process Size | 7 nm |
| Transistors | 15,200 million |
| Die Size | 4x 74 mm² |
| Package | FCLGA-4094 |
| Market | Server/Workstation |
| Production Status | Active |
| Release Date | Apr 14th, 2020 |
| Part# | 100-000000044 |
| Frequency | 1100 MHz |
| Turbo Clock | up to 3 GHz |
| Base Clock | 100 MHz |
| Multiplier | 11.0x |
| Multiplier Unlocked | No |
| Codename | Rome |
| Generation | EPYC (Zen 2 (Rome)) |
| Memory Support | DDR4 |
| ECC Memory | Yes |
| # of Cores | 32 |
| # of Threads | 64 |
| SMP # CPUs | 1 |
| Cache L1 | 64 KB (per core) |
| Cache L2 | 512 KB (per core) |
| Features | MMX, EMMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, ABM, BMI1, BMI2, FMA3, AES, RdRand, SHA, ADX, CLMUL, F16C, Real, Protected, SMM, FPU, NX bit, SMT, AMD-Vi, AMD-V, SME, TSME, SEV, x2APIC, SenseMi, Boost 2 |
| Notes | L3 Cache is split into two slices of 16 MB per CCX serving eight Zen 2 cores, for a total of 32 MB per die, 128 MB per socket. |
| Rated Speed | 3200 MT/s |
| Memory Bus | Eight-channel |
| Memory Bandwidth | 204.8 GB/s |
| PCI-Express | Gen 4, 128 Lanes (CPU only) |
| Cache L3 | 32 MB (per die) |
| I/O Process Size | 14 nm |
| I/O Die Size | 416 mm² |
| I/O Transistors | 9,100 million |
| # of CCDs | 4 |
| Cores per CCD | 8 |
| Total L3 | 128 MB |
| Benchmark rank | 94 |
| Benchmark samples | 1 |
| Benchmark price | 0 |
| Benchmark category | Server |
| Benchmark date | 2022-10-01 |
| Benchmark TDP (W) | 85 |
| Benchmark base (MHz) | 1100 |
| Benchmark turbo (MHz) | 3000 |
| Benchmark cores | 32 |
| Benchmark threads per core | 2 |
| Benchmark threads | 64 |