CPU Wiki

EPYC 7352

AMD · AMD Socket SP3 · Server/Workstation · 2019

Key facts

Production status: Active
Release date: 2019-08-07
Cores / Threads: 24 / 48
Base clock: 2300 MHz
Turbo clock: 3200 MHz
TDP: 155 W
Process: 7 nm
Codename: Rome
Generation: EPYC (Zen 2 (Rome))

All available specs

FieldValue
nameEPYC 7352
SocketAMD Socket SP3
FoundryTSMC
Process Size7 nm
Transistors15,200 million
Die Size4x 74 mm²
PackageFCLGA-4094
MarketServer/Workstation
Production StatusActive
Release DateAug 7th, 2019
Part#100-000000077
Frequency2.3 GHz
Turbo Clockup to 3.2 GHz
Base Clock100 MHz
Multiplier23.0x
Multiplier UnlockedNo
CodenameRome
GenerationEPYC (Zen 2 (Rome))
Memory SupportDDR4
ECC MemoryYes
# of Cores24
# of Threads48
SMP # CPUs2
Cache L196 KB (per core)
Cache L2512 KB (per core)
FeaturesMMX, EMMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, ABM, BMI1, BMI2, FMA3, AES, RdRand, SHA, ADX, CLMUL, F16C, Real, Protected, SMM, FPU, NX bit, SMT, AMD-Vi, AMD-V, SME, TSME, SEV, x2APIC, SenseMi, Boost 2
NotesL3 Cache is split into two slices of 16 MB per CCX serving three Zen 2 cores, for a total of 32 MB per die, 128 MB per socket.
Rated Speed3200 MT/s
Memory BusEight-channel
Memory Bandwidth204.8 GB/s
Launch Price$1,350
PCI-ExpressGen 4, 128 Lanes (CPU only)
Cache L332 MB (per die)
Configurable TDP180 W
I/O Process Size14 nm
I/O Die Size416 mm²
I/O Transistors9,100 million
# of CCDs4
Cores per CCD6
Total L3128 MB
Per-Socket PCI-ExpressGen 4, 64 Lanes
Benchmark rank78
Benchmark samples4
Benchmark price1828.02
Benchmark categoryServer
Benchmark socketSP3
Benchmark date2021-08-01
Benchmark TDP (W)155
Benchmark base (MHz)2300
Benchmark turbo (MHz)3200
Benchmark cores24
Benchmark threads per core2
Benchmark threads48