CPU Wiki

EPYC 7252

AMD · AMD Socket SP3 · Server/Workstation · 2019

Key facts

Production status: Active
Release date: 2019-08-07
Cores / Threads: 8 / 16
Base clock: 3100 MHz
Turbo clock: 3200 MHz
TDP: 120 W
Process: 7 nm
Codename: Rome
Generation: EPYC (Zen 2 (Rome))

All available specs

FieldValue
nameEPYC 7252
SocketAMD Socket SP3
FoundryTSMC
Process Size7 nm
Transistors7,600 million
Die Size2x 74 mm²
PackageFCLGA-4094
MarketServer/Workstation
Production StatusActive
Release DateAug 7th, 2019
Part#100-000000080
Frequency3.1 GHz
Turbo Clockup to 3.2 GHz
Base Clock100 MHz
Multiplier31.0x
Multiplier UnlockedNo
CodenameRome
GenerationEPYC (Zen 2 (Rome))
Memory SupportDDR4
ECC MemoryYes
# of Cores8
# of Threads16
SMP # CPUs2
Cache L164 KB (per core)
Cache L2512 KB (per core)
FeaturesMMX, EMMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, ABM, BMI1, BMI2, FMA3, AES, RdRand, SHA, ADX, CLMUL, F16C, Real, Protected, SMM, FPU, NX bit, SMT, AMD-Vi, AMD-V, SME, TSME, SEV, x2APIC, SenseMi, Boost 2
NotesThe integrated memory controller is, "performance optimized for four channels," per AMD's specification. While the appropriate number of DIMMs are still supported for octo-channel support, per-socket bandwidth cannot exceed that of quad-channel bandwidth.L3 Cache is split into two slices of 16 MB per CCX serving two Zen 2 cores, for a total of 32 MB per die, 64 MB per socket.
Rated Speed3200 MT/s
Memory BusEight-channel
Memory Bandwidth85.3 GB/s
Launch Price$475
PCI-ExpressGen 4, 128 Lanes (CPU only)
Cache L332 MB (per die)
Configurable TDP150 W
I/O Process Size14 nm
I/O Die Size416 mm²
I/O Transistors9,100 million
# of CCDs2
Cores per CCD4
Total L364 MB
Per-Socket PCI-ExpressGen 4, 64 Lanes
Benchmark rank357
Benchmark samples3
Benchmark price380.03
Benchmark categoryServer
Benchmark socketSP3
Benchmark date2021-05-01
Benchmark TDP (W)120
Benchmark base (MHz)3100
Benchmark turbo (MHz)3200
Benchmark cores8
Benchmark threads per core2
Benchmark threads16