Key facts
Production status: End-of-life
Release date: 20-Jun
Cores / Threads: 5 / 5
Base clock: 800 MHz
Turbo clock: 2800 MHz
TDP: 7 W
Process: 10 nm
Codename: Lakefield
Generation: Core i3 (Lakefield)
All available specs
| Field | Value |
|---|---|
| name | Core i3-L13G4 |
| Foundry | Intel |
| Process Size | 10 nm |
| Transistors | 4,050 million |
| Die Size | 82 mm² |
| Package | FC-CSP2H |
| Market | Mobile |
| Production Status | End-of-life |
| Release Date | 20-Jun |
| Part# | SRH4X, SRJGC |
| Frequency | 800 MHz |
| Turbo Clock | up to 2.8 GHz |
| Base Clock | 100 MHz |
| Multiplier | 8.0x |
| Multiplier Unlocked | No |
| TDP | 7 W |
| Codename | Lakefield |
| Generation | Core i3 (Lakefield) |
| Memory Support | LPDDR4X |
| ECC Memory | No |
| # of Cores | 5 |
| # of Threads | 5 |
| SMP # CPUs | 1 |
| Integrated Graphics | UHD Graphics 48EU |
| Cache L1 | 80 KB |
| Cache L2 | 512 KB |
| Features | MMX, SSE, SSE2, SSE3, SSSE3, SSE4.2, AES-NI, SHA, F16C, BMI, BMI2, EM64T, VT-x, VT-d, EPT, EIST, TSX, XD-bit, Rdrand, TBT2.0, TBMT 3.0 |
| Notes | FC-CSP - Flip-chip chip-scale-package which utilizes Foveros 3D die stacking to include the chipset, SoC, and package-on-package LPDDR4x.SRH4X - 8 GB LPDDR4xSRJGC - 4 GB LPDDR4xAVX, TXT, MPX disabled on "Sunny Cove" P-Core to match "Tremont" E-Cores.UHD Graphics (Gen 11) dynamic frequency: 200-500 MHz |
| Rated Speed | 4267 MT/s |
| Memory Bus | Single-channel |
| Memory Bandwidth | 17.1 GB/s |
| tJMax | 100°C |
| Launch Price | $281 |
| PCI-Express | Gen 3, 6 Lanes (CPU only) |
| Cache L3 | 4 MB (shared) |
| Memory Capacity | 4 GB, 8 GB |
| E-Core Frequency | 800 MHz up to 1300 MHz |
| Hybrid Cores | P-Cores: 1 E-Cores: 4 |
| E-Core L1 | 64 KB (per core) |
| E-Core L2 | 1.5 MB (shared) |
| Base Die Process | 22 nm |
| Base Die Transistors | 605 million |
| Base Die Size | 92 mm² |
| All Core Turbo | 1300 MHz |
| Bus Speed | 4 GT/s |
| Packaged Memory | LPDDR4x |